The present disclosure relates to a semiconductor package, in particular, to a method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and/or a fan-out panel level package fabricated thereby.
As an integration density of a semiconductor chip increases, its size is gradually decreased. However, a distance between bumps on a semiconductor chip may be a fixed parameter that is given by international standards of the Joint Electron Device Engineering Council (JEDEC). Accordingly, changing the number of bumps provided on a semiconductor chip may be limited. Also, as a semiconductor chip is shrunk, there are considerations in handling and testing the semiconductor chip. In addition, diversifying a board in accordance with a size of a semiconductor chip is a consideration. A fan-out panel level package has been proposed.